Manufacture of electronic devices comprising thin-film circuit elements

ABSTRACT

In the manufacture of an electronic device such as an active matrix display, a vertical amorphous PIN photodiode or similar thin-film diode (D) is advantageously integrated with a polysilicon TFT (TFT 1 , TFT 2 ) in a manner that permits a good degree of optimisation of the respective TFT and diode properties while being compatible with the complex pixel context of the display. High temperature processes for making the active semiconductor film ( 10 ) of the TFT more crystalline than an active semiconductor film ( 40 ) of the diode and for forming the source and drain doped regions (s 1 ,s 2 , d 1 ,d 2 ) of the TFT are carried out before depositing the active semiconductor film ( 40 ) of the diode. Thereafter, the lateral extent of the diode is defined by etching while protecting with an etch-stop film ( 30 ) an interconnection film ( 20 ) that can provide a doped bottom electrode region ( 41 ) of the diode as well as one of the doped regions (s 2 , g 1 ) of the TFT.

This invention relates to methods of manufacturing an electronic device,for example an active matrix display, comprising thin-film circuitelements that include a diode integrated with a crystalline thin-filmtransistor, the transistor having a channel area in an activesemiconductor film that is more crystalline than an active semiconductorfilm of the diode, for example an amorphous PIN photodiode. Theinvention also relates to such device structures themselves.

Examples of such devices in the form of active matrix electroluminescentdisplays are disclosed in published PCT patent applicationsWO-A-01/20591, WO-A-01/99190 and WO-A-01/99191, the whole contents ofwhich are hereby incorporated herein as reference material. In theseelectroluminescent display devices, each pixel comprises:

-   -   a light-emitting element, typically a light-emitting diode (LED)        of organic semiconductor (for example, polymer semiconductor),    -   at least two thin-film transistors (TFTs) of polycrystalline        silicon (polysilicon), whereby the LED is driven via a first,        drive TFT as addressed via the second, address TFT,    -   a thin-film storage capacitor for storing the drive signal        applied to the gate of the drive TFT via the address TFT, and    -   a light-sensing element (for example, an amorphous PIN        photodiode, or a photo-responsive polysilicon TFT) that is        responsive to the LED output to provide optical feed-back for        regulating LED operation via the drive TFT (in order to        counteract aging effects in the LED).

The present invention can be applied to, for example, the integration ofthe drive and/or address TFT with an amorphous PIN photodiode as thelight-sensing element.

As illustrated in WO-A-01/20591, WO-A-01/99190, and WO-A-01/99191, thelight-sensing element is connected:

-   -   in parallel with the capacitor, between the gate of the drive        TFT and its power supply line (source connection of the drive        TFT), and    -   between the drive signal output (drain electrode) of the address        TFT) and the power supply line (source connection of drive TFT).

In fabricating these display devices, it is generally convenient to formthe light-sensing element using common technology and process steps withthe TFTs. For this reason, it has been preferable to form thelight-sensing element as a photo-sensitive TFT structure (having itsgate of ITO or other transparent electrode material connected to itssource), or possibly as a lateral PIN diode. In each case, thelight-absorbing active semiconductor film of this photo-sensitive TFTstructure or PIN diode is provided using the same technology and processsteps as the drive and address TFTs of the pixel.

A disadvantage of this approach is that the active semiconductor film(that provides the channel area of the TFTs) is comparatively thin (forexample, with a thickness in the range of 0.04 μm to 0.101 μm). Anintrinsic silicon film of this thickness is not fully absorbing at thered end of the spectrum. As a result, different sized photo TFTs/diodesare required for red, green and blue pixels, and the photo TFT/diode forthe red is particularly large, consuming useful aperture area. Thisproblem is avoidable if vertical amorphous PIN diodes with thickersilicon are used as the light-sensing elements, but problems then ariseas to how best to integrate such vertical diodes with the TFTs in amanner compatible with the display pixel layout.

Similar problems arise with other types of display, for example with theintegration of photodiodes in pixels of an active matrix liquid-crystaldisplay (AMLCD). The whole contents of United States patent U.S. Pat.No. 5,838,308 are herby incorporated herein as reference material for anexample of a need to integrate light-sensing elements in the pixels ofan AMLCD for an optical input to the device.

It is an aim of the present invention to facilitate the integration of athin-film diode (for example a vertical amorphous PIN photodiode) with amore crystalline thin-film transistor in a manner that permits a degreeof optimisation of the respective diode and transistor properties, whileusing common process steps for their integration and while beingcompatible with even the complex pixel context of an active matrixdisplay.

According to one aspect of the present invention, there is provided amethod for the manufacture of such a device, that includes:

(a) forming on a circuit substrate the crystalline active semiconductorfilm for a channel area of the TFT, with a first process involving afirst processing temperature;

(b) forming doped source and drain regions of the TFT at ends of thechannel area with a second process involving a second processingtemperature;

(c) providing an interconnection film between an electrode area of theTFT and a diode area over which the diode is to be formed, and providingan etch-stop film on which the active semiconductor film for the diodeis to be deposited;

(d) thereafter depositing the active semiconductor film for the diodeover the interconnection film and the etch-stop film with a thirdprocess that involves a third processing temperature, this stage (d)being performed after stages (a) and (b), and the first and secondprocessing temperatures being higher than the third processingtemperature; and

(e) thereafter etching away the active semiconductor film for the diodefrom over the etch-stop to leave the active semiconductor film for thediode over the interconnection film in the diode area.

By carrying out stages (a) and (b) before stage (d), such a method inaccordance with the invention is advantageous for the TFT in permittingthe achievement of good quality crystalline material for its channelarea and of efficient source and drain regions, through the use of thehigher first and second processing temperatures. Thus, for example, goodpolysilicon TFTs can be formed using laser crystallisation of thesilicon film and laser annealing of source and drain dopant implants.The source and drain regions can be formed so as to be self-aligned withthe gate electrode of the TFT. Although stages (a) and (b) may be usedto provide a bottom-gate TFT, the invention is particularly useful withtop-gate TFTs. The TFT may be advantageously hydrogenated after stages(a) and (b) and before the lower temperature stage (d).

By carrying out stage (d) with its lower processing temperature afterthe higher temperature stages, such a method in accordance with theinvention is advantageous for providing the diode with a lesscrystalline material (for example, even an amorphous semiconductormaterial) in an appropriate thickness for the desired diodecharacteristics. Thus, for example, efficient photodiodes of a verticalPIN structure can be formed with an intrinsic hydogenated amorphoussilicon (aSi:H) film that is thicker than the polysilicon film of theTFT. Furthermore, de-hydrogenation of this diode film (which would occurif the higher temperature process stages (a) and (b) were carried outsubsequently) is avoided by performing these higher temperature processstages (a) and (b) before providing the aSi:H film of the diode. Theresulting diode may advantageously exploit a hybrid of amorphous andpolysilicon technologies Furthermore, by depositing and etching theactive semiconductor film for the diode over the etch-stop film (as wellas over the interconnection film), the layout of this semiconductor filmin the diode area can be defined without undesirable etching of otherparts of the device such as the TFT and its interconnection to thediode. Such a method in accordance with the invention permits the use ofsome common films for the TFT and the diode. Thus, for example, theinterconnection film can form gate or source/drain connections to theTFT and/or a bottom connection to the diode, whereas another film mayprovide a top connection to the diode in, for example, a display pixellayout. The interconnection film may even provide the gate electrode orsource and drain regions of the TFT and/or an electrode region of thediode. In this manner, the height of stepped increases in the topographydue to the integration of a thick vertical diode can be reduced. Thisreduces problems, for example, in providing transparent display-pixelelectrodes over the integrated diode and TFT structure.

Several basic variants are possible depending on the nature andarrangement of the etch-stop and interconnection films.

In one form, the interconnection film may comprise metal which itselfprovides the etch-stop film. In this case, the diode may have a verticalPIN diode structure formed in its active semiconductor film (as anintrinsic region between P and N electrode regions) deposited on themetal film.

In another form, for example, the etch-stop film may be an insulatingfilm that extends over the interconnection film and that has a window atthe diode area to permit contact between the interconnection film andthe active semiconductor film of the diode. With this form, theinterconnection film may be of metal. However, with this form ofetch-stop film, the interconnection may even be of semiconductormaterial that provides a bottom one of the electrode regions of thediode (for example, a P+ or N+ doped region of a PIN diode). Thus, sucha semiconductor electrode/interconnection film of the diode can beadequately protected by the insulating etch-stop film during theetch-definition of the diode layout. This permits the provision of noveldevice structures.

Thus, according to another aspect of the present invention, there isprovided an electronic device comprising thin-film circuit elements thatinclude a diode integrated with a crystalline thin-film TFT, wherein:

-   -   the TFT has at least one of its source, drain and gate formed as        a doped region of a crystalline semiconductor film that is more        crystalline than an active semiconductor film of the diode;    -   the doped region of the crystalline semiconductor film extends        from the TFT to provide a bottom electrode region of the diode        that is thereby interconnected with the said one of the TFT        source, drain and gate; and    -   the diode has its said active semiconductor film on the        crystalline semiconductor film at a window in an insulating        etch-stop film that extends over the crystalline semiconductor        film and over at least a portion of the crystalline TFT, the        active semiconductor film of the diode having a lateral extent        that terminates on the insulating etch-stop film.

Various advantageous features and feature-combinations in accordancewith the present invention are set out in the appended claims. These andothers are illustrated in embodiments of the invention that are nowdescribed, by way of example, with reference to the accompanyingdiagrammatic drawings, in which:

FIG. 1 is a circuit diagram of a pixel circuit of an active-matrixelectroluminescent display device, illustrating an example of thecontext in which the present invention can be used;

FIG. 2 is a cross-sectional view of parts of one pixel structure formedon a circuit substrate of such an active-matrix electroluminescentdisplay device, in one particular embodiment of the invention;

FIGS. 3 to 7 are a cross-sectional view of a TFT and diode part of apixel structure similar to that of FIG. 2 at successive stages in itsmanufacture by a method in accordance with the invention; and

FIGS. 8 to 13 are cross-sectional views during manufacture, of a TFT anddiode part of other pixel structures that can be manufactured by otherrespective methods in accordance with the invention.

It should be noted that all the Figures are diagrammatic. Relativedimensions and proportions of parts of these Figures have been shownexaggerated or reduced in size, for the sake of clarity and conveniencein the drawings. The same reference signs are generally used to refer tocorresponding or similar features in modified and different embodiments.

FIG. 1 Example of the Display Pixel Circuit

The circuit of FIG. 1 illustrates just one pixel of a pixel array of anactive-matrix electroluminescent display device of the general type thatis disclosed in, for example, WO-A-01/20591, WO-A-01/99190 andWO-A-01/99191. FIG. 1 illustrates a particularly simple example of pixelcircuit, whereas other more complex pixel circuits with more than twoTFTs are also known. It will be understood that the present inventionmay be applied not only to the simple circuit of FIG. 1, but also tothese more complex pixel circuits.

As illustrated in FIG. 1, each pixel comprises:

-   -   a light-emitting element 500, typically a light-emitting diode        (LED) of organic semiconductor (for example, polymer        semiconductor),    -   at least, two polysilicon thin-film transistors (namely a drive        TFT1 and an address TFT2), whereby the LED 500 is driven via the        drive TFT1 as addressed via the address TFT2,    -   a thin-film storage capacitor Cs for storing the drive signal        applied to the gate of drive TFT1 via address TFT2, and    -   an amorphous PIN photodiode D that is responsive to the light        output 501 of the LED 500 and is used for regulating the        operation of the LED 500 via drive TFT1 in order to counteract        aging effects in the LED 500.

The present invention is illustrated in its application to theintegration of a thick, vertical amorphous PIN photodiode D with driveTFT1 and/or address TFT2. As shown in FIG. 1, this thin-film diode D isconnected between power supply line 451 and an internal conductor line460, in parallel with the capacitor Cs. The power supply line 451 (+Vp)is connected to the source s1 of the drive TFT1), as well as to the PINdiode D and to the capacitor Cs. The conductor line 460 is connected toboth the gate g1 of drive TFT1 and the drive signal output (source s2)of the address TFT2, as well as to the PIN diode D and to the capacitorCs. The address TFT2 has its gate g2 connected to a respective rowconductor 452 of the array, and its drain d2 is connected to arespective column conductor 453 of the array. The pixel layout is suchthat the photodiode D receives part of the light output 501 from itsrespective pixel, without the pixel aperture being obscured by thecapacitor Cs, TFTs TFT1 and TFT2 and their connection conductors.

Thus, the process stages used for the integration of these thin-filmcircuit elements D, Cs, TFT1, TFT2 on a circuit substrate 100 need to becompatible with the complex pixel context of the display device. Thepresent invention permits integration of the amorphous PIN diode D withpolysilicon transistor TFT1 and/or TFT2, in a manner that permits a gooddegree of optimisation of the respective properties of the diode D andTFT, while using common process steps for their integration. Generally,the same polysilicon TFT technology and same process steps may be usedto fabricate both TFT1 and TFT2 side-by-side on the circuit substrate100, but with different TFT layouts and different connection layouts foreach TFT.

Several specific embodiments for the integration of the diode D withthese TFTs are now described with respect to the FIGS. 2 to 13. Eachspecific embodiment includes the stages of:

-   -   (a) forming on the circuit substrate 100 a crystalline active        semiconductor film 10 for the channel areas 1 of the TFTs TFT1        and TFT2, with a first process involving a first processing        temperature;    -   (b) forming doped source regions s1,s2 and drain regions d1,d2        of the TFTs at ends of the channel area, with a second process        involving a second processing temperature;    -   (c) providing an interconnection film 20 between an electrode        area of one of the TFTs and a diode area over which the diode D        is to be formed, and providing an etch-stop film 30 on which an        active semiconductor film 40 for the diode is to be deposited;    -   (d) thereafter depositing the active semiconductor film 40 for        the diode D over the interconnection film 20 and the etch-stop        film 30 with a third process that involves a third processing        temperature, this stage (d) being performed after stages (a) and        (b), and the first and second processing temperatures being        higher than the third processing temperature; and    -   (e) thereafter etching away the active semiconductor film 40 for        the diode D from over the etch-stop film 30 to leave the active        semiconductor film 40 for the diode over the interconnection        film 20 in the diode area.

Such a device manufacturing method in accordance with the invention isadvantageous for providing the TFT with good quality crystallinematerial for its channel area and with efficient source and drainregions. This is achieved through the use of the higher first and secondprocessing temperatures in stages (a) and (b). By carrying out stage (d)with its lower third processing temperature after stages (a) and (b),such a method is also advantageous for providing the diode D with a lesscrystalline material 40 (preferably even an amorphous semiconductormaterial) in an appropriate film thickness for the desired diodecharacteristics. By depositing and etching the active semiconductor film40 for the diode D over the etch-stop film 30 (as well as over theinterconnection film 20), the layout of this semiconductor film 40 inthe diode area can be defined without undesirable etching of other partsof the device such as the TFT and its interconnection to the diode D.

Such a method in accordance with the invention permits the use of one ormore common films for the diode D and TFT1 and/or TFT2, depending on thenature and arrangement of, for example, the interconnection film 20 andthe etch-stop film 30. Various specific embodiments will now bedescribed.

Embodiment of FIGS. 2 to 7

FIG. 2 illustrates the pixel structure of one embodiment of a displaydevice as manufactured by a first embodiment of a method in accordancewith the invention.

Polysilicon TFT1 and TFT2 each comprise an island of a crystallinesilicon film 10 that provides each TFT with its respective channel area.Both the TFT1 island and TFT2 island are shown in FIG. 2, beingartificially constrained into the plane of the drawing. In a practicalpixel layout, TFT1 and TFT2 would normally be in different crosssections. Both these TFTs are themselves of a known top-gateconfiguration which has its respective gate electrode g1,g2 on a gatedielectric film 2 on the silicon film 10 and which has its respectivesource s1,s2 and drain d1,d2 formed as doped regions of the film 10. Inthis embodiment, the source s1,s2 and drain d1,d2 of both TFTs have ap-type doping (P+), and both the TFTs are p-channel.

The address TFT2 has its gate g2 connected to row metallisation 452 ofthe array, and its drain d2 connected to column metallisation 453 of thearray. Its source s2 is connected by internal conductor line 460 to thecapacitor Cs, to the photodiode D, and (also via metallisation 461) tothe gate g1 of the drive TFT1. The drive TFT1 has its drain dl connectedby metallisation 450 to the bottom transparent (ITO) electrode 561 ofthe pixel LED 500. As shown in FIG. 2, these connections tometallisation pattern 450, 451, 452, 453, 461 (for example of aluminium)are made via contact windows in an inter-level insulating layer 51. Afurther insulating layer 52 separates this metallisation pattern fromthe LED pixels, except at a window where the transparent display-pixelelectrode 561 is connected to the TFT1 drain metallisation 450.

The present invention reduces the height of stepped increases in thetopography due to the integration of the thick vertical PIN diode D.This reduces problems in providing the transparent display-pixelelectrodes 561 over the integrated diode and TFT Structure. Thelight-emitting semiconductor polymer film 560 of the pixel LED 500 issandwiched between this electrode 561 and a grounded cathode electrode562.

Furthermore, the present invention (as implemented in the embodiment ofFIG. 2) provides the interconnection film 20 in an advantageous mannerfor the conductor line 460, connecting the diode D and the source s2 ofaddress TFT2.

Thus, in this embodiment, a P+ doped track region of the polysiliconfilm 10 is is used to provide this interconnection film 20 (conductorline 460).

Furthermore, a P+ region of this same film 10,20 may also provide thebottom plate of capacitor Cs. This use of the film 10,20 for the bottomplate of capacitor Cs is illustrated in the FIG. 2 embodiment. In thisparticular example, the top plate 3 of capacitor Cs is illustrated as aseparate area of the film that provides the TFT gates g1,g2. Thus, thegate dielectric film 2 may also provide the capacitor dielectric.

Thus, as illustrated in FIG. 2, a continuous P+ doped track ofpolysilicon film 10 forms the doped source s2 of TFT2, the bottom plateof capacitor Cs, the bottom electrode region 51 of PIN diode D, andtheir interconnection 20. The gate g1 of TFT1 is connected to this P+polysilicon track.

The remainder of the PIN diode D of FIG. 2 is formed on this polysiliconP+ region 51 by etch-defined regions 40 and 42 of a thick amorphousintrinsic silicon film and of a thinner amorphous N+ doped silicon film.In this embodiment, the etch-stop film 30 used during the etchdefinition of the diode D is provided by an extension of thegate-dielectric film 2. A metal film (for example of chromium) for thetop contact 45 may be present over the diode area during this etchingstage, and its contact area (and obscuration) on the diode region 42 canbe restricted later (for example, after defining the metallisationpattern 450, 451,452,453,461).

FIG. 3 illustrates stage (a) in the manufacture of this embodiment. Thesubstrate 10 is typically of a low-cost insulating material (for exampleglass, or s perhaps even an insulating polymer), having an insulatingcoating of, for example, silicon dioxide or silicon nitride providingits upper surface on which the circuit elements are formed. A siliconfilm 10. initially of amorphous material is deposited for the TFTislands and is crystallised in known manner by heating with a laser beam200. Typically, an excimer laser may be used, with a laser energy andpulse rate sufficient to melt the film 10 through most of its thickness.

The silicon film 10 typically reaches temperatures in the range of 1000°C. to 1400° C. (depending on its hydrogen content) during this lasertreatment.

FIG. 3 depicts three parts to this film 10, namely part [TFT] where aTFT (TFT1 or TFT2) will be formed, part [D] where the diode D will beformed, and part [20,460] where the TFT-diode interconnection will beformed. It should be noted that the FIG. 3 cross-section shows the part[20,460] in link-dot outline to indicate that this part [20,460] of thefilm 10 is out of the plane of the drawing. This cross-section is morerealistic for a display pixel layout than that of FIG. 2, in which bothTFT1 and TFT2, the diode D and the interconnection 20,460 were allconstrained into the plan of the drawing. In the case where the part[TFT] of FIG. 3 is for TFT2, the part [20,460] of the film 10 extendsout of the plane of the drawing while remaining integral with the parts[TFT] and [D] which are in the plan of the drawing. In a case where thepart [TFT] is for TFT1, the part [20,460] of the film 10 is not integralwith this [TFT] part of FIG. 3, but only with the part [D] which is inthe plan of the drawing.

In order to simplify the description for the subsequent FIGS. 4 to 7, itwill be assumed that FIG. 3 shows the [TFT] part of TFT2, that theseparate TFT1 island of the film 10 is also out of the plane of thedrawing, and that TFT1 is fabricated with the same process steps as thedepicted TFT2.

FIG. 4 illustrates a subsequent stage in the manufacture, afterdeposition of the gate-dielectric film 2 and a film g′ of metal.Typically, the film g′ may be of, for example, aluminium, or chromium,or silicide or another material or alloy commonly used for TFT gateelectrodes. The gates g1 and g2 are defined from the film g′ with normalphotolithographic and etching techniques.

FIG. 5 illustrates the later stage (b), in which the P+ regions s1,s2,d1,d2, 20(460) and 41 are formed in the polysilicon film 10. These P+regions are formed by implanting boron ions in the film 10 (except wheremasked by the gates g1 and g2 and any additional mask feature) and thenheating to anneal the implantation damage and activate the boron dopant.This heating step may be performed with a laser beam 201. During suchlaser treatment, the temperature of exposed areas of the silicon film 10typically exceeds 900° C. Instead of a laser beam, a rapid thermalanneal (RTA) using high-intensity light 201 may be used for this heattreatment. In this case, the exposed areas of the silicon film 10typically reach a temperature in the range of 600° C. to 900° C. In afurther alternative, a furnace anneal in the range of 350° C. to 600° C.may be used. A combination of these heating treatments may even be used.Multiple implants may also be used to form differently doped regions,for example, in a LDD (low-doped drain) structure.

These stages (a) and (b) of FIGS. 3 and 5 with their high processingtemperatures are very advantageous for the TFTs, in the achievement ofgood quality crystalline material for their channel area and ofefficient source and drain contacts. Furthermore, by using the gateelectrodes g1 and g2 as implantation masks, the P+ source and drainregions s1,s2 and d1,d2 are self-aligned with their gate electrodeg1,g2.

Either before or after this doping stage (b), a window 24 is opened inthe film 2 at the area where the PIN diode D is to formed. This window24 permits contact between the interconnection film 20 (polysilicon film2 in this embodiment) and the subsequently-deposited active diode film(amorphous intrinsic film 40 in this embodiment).

It is desirable to hydrogenate the polysilicon TFTs after depositingtheir gate dielectric 2 (i.e. after FIG. 4). This hydrogenation stage isanother treatment at a moderately high temperature, and so it is carriedout before depositing the amorphous silicon material for the diode D. Itmay typically be a thermal anneal at 300° C. to 400° C. in N₂/H₂ gas(10% H₂), or it may be a hydrogen plasma exposure at 300-400C., or acombination of both. Preferably, it should be performed after providingthe gate metal and activating the dopant since any damage introduced bythese two processes can then be passivated by the hydrogen. Therefore,preferably, this hydrogenation is performed after stages (a) and (b) andbefore stage (d), and it may be the very last process that is performedbefore the a-Si deposition stage (d).

FIG. 6 illustrates the subsequent deposition stages for the PIN diode D,when an un-doped amorphous hydrogenated silicon film 40′ is depositedfor the intrinsic region 40(I) of the PIN diode D, followed by an N+doped amorphous silicon film 42′ for the N+ region 42. These amorphousfilms 40′ and 42′ are typically deposited at a temperature in the range100° C. to 300° C. By carrying out this stage (d) with its lower thirdprocessing temperature after stages (a) and (b), the photodiode D can beformed as a vertical PIN diode structure with a good quality intrinsicamorphous semiconductor region 40 in an appropriate thickness for thedesired diode characteristics.

Thus, the thickness of the un-doped amorphous silicon film 40′ is chosenas desired for efficient absorption of the LED output 501 by theintrinsic region 40(I) of the PIN diode D, even at the red end of thespectrum. In a typical embodiment of an active matrix electroluminescentcolour display, efficient PIN photodiodes can be formed with anintrinsic amorphous silicon film that has a thickness in the range of,for example, 0.5 μm to 1.0 μm. This is much thicker than the polysiliconfilm 10 of the TFTs, which may have a thickness in the range of, forexample, 0.04 μm to 0.10 μm.

Thereafter, the lateral dimensions of the PIN diode D are defined in thefilms 42′ and 40′ with normal photolithographic and etching techniques,but using the gate-dielectric film 2 as an etch-stop 30. Thus, thisetch-stop film 2,30 prevents undesirable etching of other parts of thedevice, such as the polysilicon film 10 that forms the TFT islands andthe interconnection 20,460 to the diode D. During this etching step, atop metal film 45′ (for example of chromium) may be present over thediode area as at least part of the etchant mask. Its lateral extent canbe restricted at a subsequent stage (after defining the metallisationpattern 450, 451, 452, 453, 461) to give the desired contact area (andedge-only obscuration) of the top metal contact 45 on the diode region42.

Two unusual aspects of this embodiment are to be seen in the resultingstructure of PIN diode D, namely:

-   -   dielectric layer 2,30 is interposed between the edge of the P+        lower electrode region 41 of the PIN. diode D and its intrinsic        region 40, and    -   the P+ lower electrode region 41 of this amorphous PIN diode is        formed in the polysilicon film 10, i.e. a hybrid of        technologies.

The number of process steps and mask steps is reduced by using in thisway common films 10 and 2,30 in the TFT and diode and for theinterconnection and etch stop. Thereafter, the manufacture of the deviceis continued in known manner.

In this embodiment, the TFT gates g1 and g2 were provided before thesource/drain formation stage (b) so producing a self-aligned structure.However, the present invention may be used with non-self-aligned TFTs,in which the channel area of the film 10 is masked with, for example,photoresist during the dopant implant of the source/drain formationstage (b). Thereafter, the TFT gates g1 and g2 can be provided, forexample with the same metallisation film as used for a top metallisation420 of the PIN diode D. A separate part of this gate metallisation filmmay even form, for example, an interconnection between the topmetallisation 420 of the PIN diode D and the source s1 of the driveTFT1.

Embodiment of FIG. 8

In the embodiment of FIGS. 2 to 7 the interconnection film 20 and thebottom electrode region 41 of the diode D are formed in the polysiliconfilm 10 that provides TFT channel areas. FIG. 8 illustrates a modifiedembodiment, in which a different interconnection film 20 providesdoped-silicon gates g1 and g2 of the TFTs and the bottom electroderegion 41 of the diode D. In this case, the gate-dielectric film 2 isnot used as the etch stop film 30. This different interconnection film20 provides the conductor line 460 connecting the diode D with the gateg1 of drive TFT1. FIG. 8 shows the TFT1.

In this FIG. 8 embodiment, the TFT polysilicon film 10 is formed bylaser crystallisation, as in FIG. 3. After depositing thereon thegate-dielectric film 2, the interconnection film 20 is deposited andpatterned by photolithography and etching. Thus, in this embodiment, thefilm 20 provides both a gate film g′ for the TFTs and the bottomelectrode region 41 of the diode D. As was the case for theinterconnection of FIGS. 3 to 7, the interconnection itself between thegate g1 of TFT1 and the bottom electrode region 41 of diode D is outsidethe plane of the FIG. 8 drawing, which simply shows regions g1 and 41 atits ends.

In the FIG. 8 embodiment, this film 20 (forming the interconnectionitself, the TFT gate g1 and the diode bottom electrode region 41) may bedoped P+ in the same boron doping stage (b) as is used to form the dopedregions s1,s2 and d1,d2 of the TFTs. Thus, the TFTs may still be of theself-aligned type. Thereafter, the thin-film structure is covered withan insulating film 30 which is to provide the etch-stop (instead ofusing an extension of the gate-dielectric film 2), and the contactwindow 24 is etched therein at the diode area. Thereafter themanufacture is continued as in the embodiment of FIGS. 2 to 7.

Embodiment of FIG. 9

The embodiments so far illustrated have top-gate TFTs. FIG. 9illustrates an embodiment with bottom-gate TFTs. In this embodiment (asin FIGS. 2 to 7), the polysilicon film 10 provides the interconnection20,460 between the TFT2 and bottom electrode region 41 of the diode D,as well as providing the channel area of the TFTs.

The bottom gates g1 and g2 of the TFTs are formed (by film deposition,photolithography and etching) on the substrate 100, before stage (a) ofthe process. These gates g1 and g2 may be of metal or doped polysilicon.Then the gate-dielectric film 2 is deposited, followed by the siliconfilm 10.

By photolithography and etching, the film 10 is patterned into therequired areas for the TFT islands, the bottom electrode region 41 ofthe diode D, and the desired interconnection 20,460 between regions s2and 41. As was the case in FIGS. 3 to 8, the interconnection itself isoutside the plane of the FIG. 9 drawing, which simply shows regions s2and 41 at its ends. The film 10 is converted to polysilicon material bylaser crystallisation, as in FIG. 3.

The P+ doping of the TFT regions s1,s2 and d1,d2 and the interconnection20 and the diode region 41 is then provided by boron ion implantationand laser annealing, similar to FIG. 5 (except that the gates g1 and g2are now below the film 10). This P+ doping may be performed eitherbefore or after depositing the insulating etch-stop film 30. The contactwindow 24 is etched through both the film 30 and the film 2 in thisembodiment, either before or after this P+ doping stage. Thereafter themanufacture is continued as in the embodiments of FIGS. 2 to 8.

Embodiment of FIG. 10

The embodiment of FIG. 10 is similar to that of FIG. 9, except that ametal conductor 461 is formed at the diode area in the same processingsteps as used to provide metal bottom-gates g1 and g2 of the TFTs. Thismetal conductor 461 may be an extension of the gate g1 of TFT1, so as toconnect the interconnection 20,460 (via region 41) with the gate g1 ofTFT1. In this case, a contact window 22 is opened in the gate-dielectricfilm 2 at the diode area before depositing the silicon film 10. Themetal conductor 461 contacts through this window 22 the diode region 41that is subsequently formed in the polysilicon film 10 as in theembodiments of FIGS. 5 and 9. Thereafter the manufacture is continued asin the embodiments of FIGS. 2 to 9.

Embodiment of FIG. 11

The embodiment of FIG. 11 also comprises the metal conductor 461 formedat the diode area in the same processing steps as used to provide metalbottom-gates g1 and g2 of the TFTs. However, FIG. 11 shows TFT1 insteadof TFT2. In this case, the metal conductor 461 may be an integral partof a different interconnection film 20 (now of metal) that provides theconductor line 460 between the bottom gates g1 of the TFT1, the bottomconnection 461 to the diode D, and the bottom plate of capacitor Cs.

The further manufacturing stages may be similar to those of FIG. 10, inthat the bottom P+region 41 of the PIN diode D may be formed by a regionof the TFT polysilicon film 10. However, FIG. 11 illustrates a furthermodification in which the bottom P+ region 41 of the PIN diode D isdeposited after deposition of the insulating etch-stop film 30. In thiscase, contact window (between metal conductor 461 and diode region 41)is etched through both the insulating films 30 and 2 before depositing aP+ film 41′ (for the diode region 41), the intrinsic film 40′ (for the Iregion 40) and the N+ film 42′ or the diode region 42). In this case,the P+ region 41 may be of amorphous silicon material.

Embodiment of FIG. 12

This embodiment is similar to that of FIG. 11, in that theinterconnection of gate g1 of the drive TFT1 with the diode P+ region 41is via a metal film g1,20,461. However, in the FIG. 11 embodiment, theTFTs are of the top-gate type. Thus, FIG. 12 shows the metal gate g1(and metal conductor 461) on the gate-dielectric film 2 that isdeposited over the polysilicon active film 10 of the TFTS. FIG. 12depicts three parts to this metal film g1,20,461, namely part g1 (thegate of TFT1), part 461 where diode D will be deposited, and part 20which represents their interconnection. This interconnection part 20 ofthe film is shown in link-dot outline in FIG. 12 to indicate that itextends out of the plane of the drawing, while remaining integral withthe parts g1 and 461 which are in the plan of the drawing.

In this embodiment, no additional etch-stop film 30 is needed whenetch-defining the lateral extent of the amorphous diode regions42,40,41. Thus, the silicon etch will stop at the surface of the metalfilm g1,20,461 and at the surface of the gate-dielectric 2.

Embodiment of FIG. 13.

In the embodiments of FIGS. 11 and 12, a metal interconnection filmg1,20,461 provides the gates g1 and g2 of the TFTs and the electrodeconnection to diode region 41. The diode D was provided beside the TFTs.FIG. 13 illustrates a modification in which the diode D can be providedon and/or as the gate g1 of TFT1. A very compact structure results.

In the FIG. 13 embodiment, stages (a) and (b) are first carried out toform the doped source and drain regions in the polysilicon film 10. Thisdoping may be done before or after depositing and patterning the metalfilm 20,461 for the gate electrodes g1 and g2 and any desiredinterconnect. Thereafter a stack of the amorphous silicon films 41′, 40′and 42′ is deposited over the gates g1,g2 and over the gate-dielectricfilm 2. These films 41′, 40′ and 42′ have respective P+, I, and N+conductivities for the PIN diode D. The films 41′, 40′ and 42′ are thenetched to leave the PIN diode over the channel area of the drive TFT1,i.e. on the gate g1 of TFT1. In this case, the gate dielectric film 2and the metal film 20,461 (of g2 and any desired interconnect) serve asthe etch-stop film.

In a modification of the FIG. 13 embodiment, the P+ film can bedeposited directly on the gate dielectric film 2 and patterned to formthe gate electrodes g1 and g2 and any desired interconnect. Thereafter,an insulating film 30 may be deposited and provided with contact window24 at the diode area over the channel area of TFT1. Thereafter theamorphous silicon films 40′ and 42′ of I and N+ conductivities aredeposited and etched away except from over the TFT1 where the PIN diodeis thereby formed. During this etch-definition, the insulating film 30serves as the etch-stop, protecting the underlying g2 and anyinterconnect in the P+ film 41′, as in FIG. 8. However, in this modifiedembodiment of FIG. 13, the PIN diode D itself provides gate g1 of TFT1.

Other Embodiments Having Other Features

In the embodiments of FIGS. 2 to 13, the crystallised material of theactive silicon film 10 has been described as being “polycrystalline”.However, laser crystallisation nowadays has become such an efficientprocess that the resulting crystal grains can have dimensions comparableto the dimensions of a TFT island. Thus, in practice, the film 10 in anygiven TFT island may actually be monocrystalline material, i.e. the TFT1and/or TFT2 may have an active film 10 of (what may be termed)single-crystal polysilicon.

In the embodiments of FIGS. 2 to 13, the crystalline active silicon film10 has been described as being formed by a two-stage process, i.e.deposition of an amorphous or micro-crystalline silicon film and thenlaser crystallisation to the desired crystal grain size. However, it isalso possible to deposit the silicon film 10 directly as polycrystallinematerial. Thus, for example, polysilicon material can be depositeddirectly in stage (a) by the thermal decomposition of silane (SiH₄) inthe temperature range 580° C. to 650° C. This temperature is stillhigher than that (for example, in the range 100° C. to 300° C.) used toprovide the amorphous silicon active film 40′ for the PIN diode D.

In the embodiments of FIGS. 2 to 13, the doped source and drain regionss1,s2 and d1 ,d2 have been formed by implanting dopant into previouslyun-doped regions of the active silicon film 10 of the TFT. However, itis also possible to deposit a doped extra polysilicon film for theelectrode regions s1,s2,d1,d2,(41) etc, particularly for top-gate TFTs.This doped extra polysilicon film for the electrode regions s1 ,s2,d1,d2,(41) etc may be deposited and patterned (by photolithography andetching) either before or after the undoped active film 10. If providedbefore the film 10, the resulting top-gate TFT is sometimes termed a“staggered” configuration. If provided after the film 10, the resultingtop-gate TFT is sometimes termed a “co-planar” configuration. In eachcase, the temperature (for example, in the range 580° C. to 650° C.)used to provide the doped film is still higher than that used to providethe amorphous silicon active film 40′ for the PIN diode D.

In the embodiments of FIGS. 2 to 13, the PIN diode D was formed withamorphous silicon, particularly in its intrinsic region 40. Theresulting diode has very suitable characteristics for photosensingvisible light outputs of pixels in an active matrix colour display.However, the active diode film may be of, for example, micro-crystallinesemiconductor material. This micro-crystalline diode structure can beintegrated with a polysilicon TFT in accordance with the invention.Thus, the micro-crystalline film(s) of the diode can be deposited overone or more interconnection and etch-stop films with a processingtemperature that is less than those earlier used for the polysilicon TFTin stages (a) and (b), after which the micro-crystalline film(s) can beetched away from over the etch-stop film to leave the activemicro-crystalline film for the diode over the interconnection film inthe diode area.

In the embodiments of FIGS. 2 to 13, the PIN diode D was formed with itsP+ film 41 as the bottom electrode region. However, inverted PIN diodestructures may be used (with appropriate polarity reversals) in whichthe N+ film 42 is the bottom electrode region of the PIN diode. Thepolysilicon TFTs may be n-channel having n-type source and drain regionss1,s2 and d1,d2. In this case, for example, the bottom (N+) electroderegion of the PIN diode may be formed as part of an N+ track in thepolysilicon film that provides the source s2 of the n-channel TFT2 orthat provides the gate g1 of the n-channel TFT1.

In some pixel circuits with two polysilicon TFTs TFT1 and TFT2, one TFTmay be n-channel while the other TFT may be p-channel. in this case, theTFT2 area is masked while implanting the s1,d1 dopant of oneconductivity type for TFT1, and the TFT1 area is masked while implantingthe s2,d2 dopant of opposite conductivity type for TFT2. Both of thesedopant implants and their anneal are carried out before depositing theless crystalline and/or amorphous material 40 for the diode D.

From reading the present disclosure, other variations and modificationswill be apparent to persons skilled in the art. Such variations andmodifications may involve equivalent and other features which arealready known in the design, manufacture and use of electronic devicescomprising thin-film circuits and component parts thereof and which maybe used instead of or in addition to features already described herein.

Although claims have been formulated in this Application to particularcombinations of features, it should be understood that the scope of thedisclosure of the present invention also includes any novel feature orany novel combination of features disclosed herein either explicitly orimplicitly or any generalisation thereof, whether or not it relates tothe same invention as presently claimed in any claim and whether or notit mitigates any or all of the same technical problems as does thepresent invention.

1. A method of manufacturing an electronic device comprising thin-filmcircuit elements that include a diode (D) integrated with a crystallinethin-film transistor (TFT), the transistor having a channel area (1) inan active semiconductor film (10) that is more crystalline than anactive semiconductor film (40) of the diode, wherein the methodincludes: (a) forming on a circuit substrate (100) the crystallineactive semiconductor film (10) of the transistor with a first processinvolving a first processing temperature; (b) forming doped source anddrain regions (s1,s2, d1,d2) of the transistor at ends of the channelarea (1) with a second process involving a second processingtemperature; (c) providing an interconnection film (20) between anelectrode area (s2, g1) of the transistor and a diode area over whichthe diode (D) is to be formed, and providing an etch-stop film (30) onwhich the active semiconductor film (40′) for the diode is to bedeposited; (d) thereafter depositing the active semiconductor film (40′)for the diode over the interconnection film (20) and the etch-stop film(30) with a third process that involves a third processing temperature,this stage (d) being performed after stages (a) and (b), and the firstand second processing temperatures being higher than the thirdprocessing temperature; and (e) thereafter etching away the activesemiconductor film (40′) for the diode from over the etch-stop film (30)to leave the active semiconductor film (40) for the diode (D) over theinterconnection film (20) in the diode area.
 2. A method according toclaim 1, wherein the etch-stop film (30) is an insulating film (2, 300that extends over the interconnection film (20) and that has a window(24) at the diode area to permit contact between the interconnectionfilm and the active semiconductor film of the diode.
 3. A methodaccording to claim 2, wherein the diode has its active semiconductorfilm (40) forming an intrinsic region between P and N electrode regions(41, 42) of a vertical PIN diode structure, and wherein theinterconnection film (20) comprises a doped region (P+) that is formedin stage (b) in a semiconductor film (10) together with the doped sourceand drain regions (s1,s2, d1,d2) of the transistor and a bottom one (41)of the P and N electrode regions of the PIN diode.
 4. A method accordingto claim 3, wherein regions of the crystalline active semiconductor film(10) provided in stage (a) are doped in stage (b) to provide the sourceand drain regions of the transistor, the bottom one of the P and Nelectrode regions of the PIN diode, and the interconnection filmtherebetween.
 5. A method according to claim 3, wherein at least aportion of the interconnection film (20) is provided on agate-dielectric film (2) on the crystalline active semiconductor film(10) to form a doped-semiconductor top gate electrode (g1) of thetransistor which is thereby interconnected with the bottom one (41) ofthe P and N electrode regions of the PIN diode.
 6. A method according toclaim 5, wherein the PIN diode is formed on the gate-dielectric film onthe crystalline active semiconductor film of the transistor.
 7. A methodaccording to both claim 4 and claim 5, wherein the electronic devicecomprises first and second crystalline thin-film transistors (TFT1,TFT2) integrated with the PIN diode by means of the same interconnectionfilm (20), and wherein the interconnection film (20) provides the bottomone (41) of the P and N electrode regions of the PIN diode, the top gateelectrode (g1) of the first transistor, and/or the source and drainregions (s2, d2) of the second transistor.
 8. A method according toclaim 1, wherein the interconnection film (20, 461) comprises metalwhich itself provides the etch-stop film (30), and the diode has avertical PIN diode structure formed in its active semiconductor film asan intrinsic region between P and N electrode regions.
 9. A methodaccording to claim 8, wherein at least a portion of the etch-stopinterconnection film is provided on a gate-dielectric film (2) on thecrystalline active semiconductor film to form a top gate electrode (g1)of the transistor which is thereby interconnected with a bottom one (41)of the P and N electrode regions of the PIN diode.
 10. A methodaccording to claim 9, wherein the PIN diode is formed on thegate-dielectric film on the crystalline active semiconductor film of thetransistor.
 11. A method according to claim 9 or claim 10, wherein theelectronic device comprises first and second crystalline thin-filmtransistors (FT1, TFT2) integrated with the PIN diode by means of thesame interconnection film (20, 461), and wherein the interconnectionfilm connects the bottom one (41) of the P and N electrode regions ofthe PIN diode, the top gate electrode (g1) of the first transistor, andthe source region (s2) of the second transistor.
 12. A method accordingto claim 7 or claim 11, wherein the electronic device comprises anactive-matrix electroluminescent display with a light-emitting diode(500, LED) in each pixel, and wherein the light-emitting diode is drivenvia the first transistor (TFT1) as addressed via the second transistor(TFT2).
 13. A method according to any one of the preceding claims,wherein the crystalline semiconductor film (10) is subjected to ahydrogenation process that is performed after stages (a) and (b) andbefore stage (d).
 14. A method according to any one of the precedingclaims, wherein the crystalline semiconductor film (10) is formed instage (a) by crystallising a deposited semiconductor film using laserheating (200) of the film.
 15. A method according to any one of thepreceding claims, wherein the doped source and drain regions are formedin stage (b) by an ion implant of dopant in the crystallinesemiconductor film and by annealing (201) the implanted dopant.
 16. Anelectronic device comprising thin-film circuit elements that include adiode integrated with a crystalline thin-film transistor, wherein: thetransistor has at least one of its source, drain and gate electrodesformed as a doped region (s2, g1) of a crystalline semiconductor film(10, 20) that is more crystalline than an active semiconductor film (40)of the diode, the doped region (s2, g1) of the crystalline semiconductorfilm extends from the transistor to provide a bottom electrode region(41) of the diode that is thereby interconnected with the said one (s2,g1) of the transistor source, drain and gate electrodes, and the diodehas its said active semiconductor film (40) on the crystallinesemiconductor film (10, 20) at a window in an insulating etch-stop film(2, 30) that extends over the crystalline semiconductor film and over atleast a portion of the crystalline thin-film transistor, the activesemiconductor film (40) of the diode having a lateral extent thatterminates on the insulating etch-stop film.
 17. A device according toclaim 16, wherein the diode has a vertical PIN structure having its saidactive semiconductor film as an amorphous intrinsic region (40) stackedbetween P and N electrode regions, and wherein the insulating etch-stopfilm (2, 30) extends between the bottom one (41) of the P and Nelectrode regions and the amorphous intrinsic region (40) at the lateraledge of the PIN diode.
 18. A device according to claim 16 or claim 17,and comprising any ot the additional device features resulting from theuse of any of the methods set out in any one of claims 4 to 7 or 11 to15.